The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device including a recess gate.
As semiconductor devices become highly-integrated, a cell transistor channel length has decreased and an ion implantation doping concentration of a substrate has increased, resulting in an increased junction leakage induced by an increased electric field. Thus, it has become difficult to secure a refresh characteristic of a device with a typical planar transistor structure.
A recess gate process has been introduced to overcome such a difficulty. The recess gate process includes etching a certain portion of an active region of a substrate such that a gate is formed over a recess. Thus, the cell transistor channel length is increased and the ion implantation doping concentration is decreased, resulting in an improved refresh characteristic. Furthermore, a bulb type recess gate process has been introduced to further increase the channel length by forming a recess in bulb type structure. Thus, the refresh characteristic of the device has been further improved.
FIGS. 1A to 1E illustrate cross-sectional views of a typical method for fabricating a semiconductor device including a recess gate.
Referring to FIG. 1A, field oxide layers 12 are formed in a substrate 11. The field oxide layers 12 define an active region and a field region. An oxide-based hard mask 13 is formed over the substrate 11. The oxide-based hard mask 13 functions as a barrier when etching a subsequent recess. The oxide-based hard mask 13 is used as a hard mask because the oxide-based hard mask 13 reduces damage on the substrate 11. The oxide-based hard mask 13 is formed to a small thickness to minimize a loss of the field oxide layers 12 during a subsequent removal process of the oxide-based hard mask 13. A photoresist pattern 14 defining recess regions is formed over the oxide-based hard mask 13.
Referring to FIG. 1B, the oxide-based hard mask 13 is etched using the photoresist pattern 14 as a mask. Reference denotation 13A refers to an oxide-based hard mask pattern 13A.
Referring to FIG. 1C, the photoresist pattern 14 is removed. The substrate 11 is then etched using the oxide-based hard mask pattern 13A as a barrier to form recesses 15. The recesses 15 may each include a bulb type recess configured with an upper portion having a vertical profile and a bottom portion having a rounded profile. The upper portion having the vertical profile may be referred to as a neck pattern 15A and the bottom portion having the rounded profile may be referred to as a bulb pattern 15B. The oxide-based hard mask pattern 13A functioning as a barrier is often damaged during the etch process for forming the recesses 15. At this time, the field oxide layers 12 including substantially the same material as the oxide-based hard mask pattern 13A are also damaged. Reference numeral 12A refers to remaining field oxide layers 12A.
Referring to FIG. 1D, the oxide-based hard mask pattern 13A is removed using a wet cleaning process. At this time, the remaining field oxide layers 12A including substantially the same material as the oxide-based hard mask pattern 13A are further damaged. Reference numeral 12B refers to residual field oxide layers 12B.
That is, the field oxide layers 12 are excessively damaged two times during the process for forming the recesses 15 shown in FIG. 1C and the removal process of the oxide-based hard mask pattern 13A shown in FIG. 1D because the oxide-based hard mask pattern 13A and the field oxide layers 12 include substantially the same material. The excessive damage of the field oxide layers 12 may cause deteriorated device characteristics. Examples of the deteriorated device characteristics include a leaning event where a passing gate over the residual field oxide layers 12B collapses, reduction in a word line cap value between a gate and a passing gate on an active region, and reduction of a refresh characteristic of a gate on an active region due to polysilicon filled in the damaged portions of the residual field oxide layers 12B by a subsequent gate formation process.
Referring to FIG. 1E, a gate insulation layer (not shown) is formed over the resultant structure. A polysilicon layer 16 for forming gate patterns is formed over the gate insulation layer. At this time, differences in height occur at an upper surface of the polysilicon layer 16 due to the recesses 15 and the damaged portions of the residual field oxide layers 12B. The differences in height may cause a seam in a subsequent metal layer for forming subsequent gate patterns, to be formed over the polysilicon layer 16. Thus, deteriorated device characteristics are generated such as a self-aligned contact (SAC) limitation.
Although not shown, subsequent processes include forming a metal layer and a gate hard mask over the polysilicon layer 16 with the differences in height, and selectively etching the gate hard mask, the metal layer, and the polysilicon layer 16 to form gate patterns.
According to the typical method for fabricating the semiconductor device, the substrate 11 may be prevented from damage when using the oxide-based hard mask pattern 13A as a mask for forming the recesses 15. However, the field oxide layers 12 are excessively damaged during the process for forming the recesses 15 and the removal process of the oxide-based hard mask pattern 13A because the oxide-based hard mask pattern 13A includes substantially the same material as the field oxide layers 12. Thus, the device characteristic is deteriorated. The device characteristics are also deteriorated due to the differences in height at the upper surface of the polysilicon layer 16 for forming the gates, the differences in height generated by the recesses 15 and the damaged residual field oxide layers 12B.